The present invention relates to an improved method and means for transferring data of a partial word size from a central processing unit (CPU) to a main storage unit having data stored in a larger, full word size with single bit error correction (ECC) code bits appended thereto. Such systems employ a Read-Modify-Write (RMW) type of operation characterized by first reading a selected full word from storage, replacing corresponding bits of the full word with the partial word bits transferred from the CPU, and writing the modified full word back into storage. When error correction is provided in such systems, the selected full word is checked for errors and corrected if a single bit error exists; then the corrected word is modified by the CPU bits, new ECC bits are generated and the corrected, modified word and ECC bits are written into storage.
The sequential steps of checking and correcting errors prior to modifying the selected full word significantly reduces system performance.
Various tradeoffs in this system environment are discussed in detail at page 157 of the article "Purge Your Memory Array of Pesky Error Bits" by R. Korody and D. Roaum appearing in EDN May 20, 1980 at pages 153-158. This article also includes a detailed discussion of error detection and correction circuits based upon Hamming code principles. However no satisfactory solution is offered relative to the system inefficiency caused by the sequential steps discussed above.
One approach is to perform the ECC on the smaller, CPU partial word size and to write partial words to storage (if the storage system permits) rather than full words; but this results in a more costly storage system since more check bits are required.